#### Highlights

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We investigate a new approach enhancing the carrier mobility in Si-MOSFETs with h-BN buffer layer.

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With the integration of hBN, the mobility increases an order of magnitude than that of usual Si-MOSFETs.

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The density dependent behavior is very different from that of the usual Si-MOSFET.

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The room temperature mobility is also much enhanced due to the relatively high OP energy of h-BN.

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With the enhanced electron mobility, the Si-MOSFET with h-BN layer has the potential for development of high speed devices.

## Abstract

We theoretically investigate a new approach enhancing the carrier mobility in Si-MOSFET structures. We introduce the integration of a h-BN to decorate the SiO_{2} dielectric (denoted as SiO_{2}/hBN/Si), taking advantage of its defect-free and smooth surface. The density and temperature dependent mobilities for the Si-MOSFET with a h-BN buffer layer are calculated by using a semiclassical Boltzmann theory including the scatterings by screened charged impurity and surface roughness which are inevitably presented in the environment of 2D carriers and dominant mechanisms that limit the carrier transport in Si-MOSFET at relatively low temperatures. Theoretical calculation reveals that the mobility of the system with the h-BN buffer layer monotonically increases with carrier density, which is different from the system without the buffer layer where the mobility has a maximum at an intermediate carrier density. We find that for the system with a 50 nm thick h-BN layer the mobility is 10 times higher than the system without the h-BN layer. Since high-*k* dielectrics can lead to enhanced mobility through dielectric screening we can achieve even higher mobility by using h-BN decorated HfO_{2} as gate dielectric in Si-MOSFETs compared to SiO_{2}/hBN/Si.

An important recent development in the physics and materials science is the successful fabrication of GaAs based two dimensional (2D) systems by the modulation doping technique [1]. The introduction of modulation doping technique as well as the continuous improvement in purity, growth, fabrication, and processing techniques has led to roughly four orders of magnitude increase in the low temperature 2D carrier mobility in modulation-doped GaAs–AlGaAs quantum structures to $\mathrm{}{\mathrm{}}^{\mathrm{}}\phantom{\rule{0.25em}{0ex}}{}^{\mathrm{}}$[2]. This low-temperature mobility enhancement in GaAs based 2D systems has been possible entirely through the systematic suppression of charged impurity scattering and interface roughness scattering in GaAs–AlGaAs quantum structures [3] and [4].

While there has been extensive research on 2D systems in the silicon-metal oxide semiconductor field effect transistors (Si-MOSFETs) over the last several decades, the mobility of Si-MOSFET increases only factor of 5 compared to the amazing four orders of magnitude increase of GaAs based modulation doped 2D systems during the same period. In the Si-MOSFETs mobile carriers are confined at the interface between Si and a higher band gap barrier material (i.e., SiO_{2}) which introduces inevitable disorder at the Si–SiO_{2} interface and limits the carrier mobility in these devices [3], [4] and [5]. In the usual SiO_{2}–Si-MOSFETs the carrier mobility at low carrier density is limited by charged impurity scattering located near the interface. At higher carrier densities, however, surface roughness and defect scattering associated with the Si–SiO_{2} interface become dominant, reducing carrier mobility with increasing density. The 2D mobility in SiO_{2}–Si-MOSFETs therefore has a maximum value at some intermediate carrier density (${\mathrm{}}^{\mathrm{}}\phantom{\rule{0.25em}{0ex}}{}^{\mathrm{}}$).

To reduce the interface disorder scattering, recently, a new technique for Si(111) crystalline interfaces has been demonstrated in which Si interface is passivated with a monolayer of hydrogen and the barrier material is a vacuum [6]. The fabricated Si-vacuum FET, where an electric field is applied through an encapsulated vacuum cavity instead of the usual SiO_{2} as in a Si-MOSFET, allows the 2DES to be gated on a hydrogen-passivated Si surface. The strong scattering potential associated with the disordered Si–SiO_{2}interface in the usual Si-MOSFET geometry being absent at the H-passivated Si-vacuum interface, the carrier mobility is expected to be higher in this new 2D system compared with the extensively studied SiO_{2}–Si-MOSFET system. With this technique the peak electron mobility of Si(111)-vacuum FET, indeed, is increased by factor of 4, compared to that of SiO_{2}–Si(111) MOSFETs [7]. However, due to the crystalline stability of the surface only Si(111) vacuum FETs have been fabricated [6].

In this paper, we propose a new approach enhancing the carrier mobility in Si-MOSFETs, which may be analogous to the modulation doping method in GaAs based 2D systems [1]. We introduce the integration of a hexagonal boron nitride (h-BN) to decorate the SiO_{2} dielectric (denoted as SiO_{2}/hBN/Si), taking advantage of its defect-free and smooth surface. It is expected that hBN/Si interface would have much lower disorder than the generic SiO_{2}/Si interface that has almost universally been studied so far experimentally. This expectation has, in fact, been spectacularly borne out by the recent experiments where graphene on h-BN substrates has been shown to have substantially higher (by roughly one order of magnitude or more) carrier mobility than graphene samples on the standard SiO_{2} substrates [8],[9] and [10]. Potential advantages of the proposed SiO_{2}/hBN/Si-MOSFET structures are the reduction of interface roughness and dangling bond scattering as well as the spatial separation of the charged impurities from 2D carriers, which may lead to very high 2D mobilities not achievable in SiO_{2}/Si-MOSFET structures. Due to the reduction of the surface roughness scattering, the mobility in the h-BN decorated MOSFET should, in principle, be a monotonically increasing function with the carrier density as seen in the GaAs modulation doped systems [2]. We also show that the mobility of Si-MOSFETs can be enhanced further with the integration of high-*k* HfO_{2} and 2D h-BN, taking the advantage of the suppression of impurity scattering from dielectric screening. The expected mobilities of this system should go over 100,000 cm^{2}/Vs, much higher than the currently published best samples of $\mathrm{}\mathrm{}\phantom{\rule{0.25em}{0ex}}{}^{\mathrm{}}$ [11]. With this enhanced electron mobility, the Si- MOSFETs with h-BN buffer layer has the potential for development of high speed devices. It is also possible to observe new physics (such as fractional quantum Hall effect) in Si-MOSFETs since higher mobility has led invariably to the discovery of new phenomena.

It is well known that the long-range charged impurity scattering from charged centers located near Si/SiO_{2}interface and the short-range surface-roughness scattering due to surface asperities are dominant scattering mechanisms, respectively, at the low and the high carrier density regimes in Si-MOSFETs at low temperatures [3], [4] and [5]. Usually the charged acceptors in the bulk silicon play little role as scatterers except at extremely small electron concentrations due to its relatively small density. There are many more oxide charges at or near the interface of SiO_{2} and Si in most samples. Since the charged impurity scattering decreases exponentially with increasing distance between the charged centers and the carriers in 2D inversion layer [4] and [12], interposing a layer of h-BN between SiO_{2} and Si can reduce the charged impurity scattering. Thus, h-BN layer will weaken the effect of Coulomb scattering with increasing h-BN thickness, resulting in the improvement of carrier mobility. Furthermore, since h-BN is known to be relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure [8] and [9], the atomically planar surface should also suppress surface roughness scattering at h-BN/Si interface, where 2D inversion layer is formed in Si-MOSFET system [8] and [9]. The dielectric properties of h-BN are similar to those of SiO_{2}, allowing the use of h-BN as a decorated gate dielectric with no loss of functionality.

In order to calculate the low-temperature 2D electron mobility we have carried out a microscopic transport calculation using the Boltzmann transport theory. We calculate the mobility in the presence of randomly distributed Coulomb impurity charges located at the SiO_{2}–h-BN interface with the electron–impurity interaction being screened by the 2D electron gas in the random-phase approximation (RPA) and surface roughness scattering [4] and [12]. The mobility is given by μ=eτ/m$$ where *m* is the carrier effective mass, and *τ* is the energy averaged finite temperature scattering time. The energy dependent scattering time is given by [3] and [4]

where

_{E}_{k}=*ℏ*^{2}k^{2}/2m${}_{}{\mathit{}}^{\mathrm{}}{}^{\mathrm{}}\mathrm{}$ is the electron energy,

〈|U(q)|^{2}〉${}^{\mathrm{}}$ the scattering potential, and

ε(q)$$ the 2D static RPA dielectric function or the screening function

[4]. The scattering potential for the charged impurity scattering with impurity density

*N*_{i} is given by

where

*F*(

*q*) is the form factor arising from the finite width of the 2D layer

[3] and

[13], and

V(q)=(2πe^{2}/κq)e^{−qd}$\mathrm{}{}^{\mathrm{}}{}^{\mathit{}}$ with

*κ* being the background dielectric constant, which explicitly takes into account the fact that a spatial separation of ‘

*d*’ may exist between the 2D electron layer and the charged impurities. For the scattering by the surface roughness

[3]where

Δ$$ is the average displacement of the interface and

Λ$$ is of the order of the range of its spatial variation in the direction parallel to the surface, and

*k*_{F} and

*E*_{F} are the Fermi wave vector and Fermi energy, respectively. We note that the 2D Fermi energy (

*E*_{F}) is given by

${}_{}{\mathit{}}^{\mathrm{}}{}_{}^{\mathrm{}}\mathrm{}$. It is obvious that the scattering time exponentially depends on

*d*, the average distance between interfacial charged impurities and electrons in the inversion layer. So we can expect a significant improvement of mobility attributed to the increasing

*d* when 2D h-BN is interposed between SiO

_{2} and Si. Alternatively, high-

*κ*materials have large dielectric constant which can lead to enhanced transport properties through dielectric screening, and this was indicated in Ref.

[14].

Fig. 1(a) shows the calculated results of temperature-dependent mobility in Si-MOSFETs. We consider possible mechanisms that would contribute to limiting the mobility: charged impurity scattering, surface roughness scattering, and acoustic phonon scattering. In this calculation, we use the following parameters: the density of charged impurities is ${}_{}\mathrm{}{\mathrm{}}^{\mathrm{}}\phantom{\rule{0.25em}{0ex}}{}^{\mathrm{}}$ located at *d*=5 nm from the electrons in the silicon inversion layer, the mean square height Δ$$ and the lateral spatial decay rate Λ$$ are 1.9 Å and 26 Å respectively. The electron density in the inversion layer, $\mathrm{}{\mathrm{}}^{\mathrm{}}\phantom{\rule{0.25em}{0ex}}{}^{\mathrm{}}$ , is used. For comparison we show the calculated resistivity from the acoustic phonon scattering [3] and [15]. It is obvious that at relatively lower temperatures, the role of acoustic phonon is negligible, and the total mobility is mainly determined by charged impurity scattering and surface roughness scattering. At temperatures lower than 20 K, the total mobility is almost limited exclusively by charged impurity scattering while at higher temperatures the role of surface roughness scattering becomes more important. However, this result can be seriously affected by the selection of electron concentration *n*. As we mentioned at the beginning of this paper, the long-range charged impurity scattering and the short-range surface-roughness scattering dominate, respectively, in the low and the high carrier density regimes of transport in Si-MOSFETs, and it is clearly shown in Fig. 1(b), which gives an electron density-dependent mobility in this system at a temperature of 0.25 K. Thus the proportion of surface roughness scattering and charged impurity scattering varies under different conditions, but these are dominant mechanisms that limit the mobility in Si-MOSFETs at low temperatures.

Fig. 1.

(Color online) (a) Calculated results of temperature-dependent mobility limited by three different scattering mechanisms in Si-MOSFET. (b) Theoretical mobility as a function of density in Si-MOSFET at 0.25 K. High (low)-density mobility is limited by the surface-roughness *μ*_{sur} (charged impurity *μ*_{im}) scattering.

In Fig. 2 we show that interposing a layer of h-BN between SiO_{2} and Si (i.e., SiO_{2}/hBN/Si structure) can effectively reduce the effect of these two scattering mechanisms, resulting in an enhancement of the device performance. Fig. 2(a) shows the resistivity as a function of the thickness of h-BN layer for the SiO_{2}/hBN/Si systems. We assume that all the impurities are located at the hBN/SiO_{2} interface with the same impurity density as in the SiO_{2}/Si system. When increasing the thickness of h-BN layer, only the distance between the charged impurities and carriers in the silicon inversion layer increases, thus as expected the resistivity decreases monotonically with thickness. This assumption may be somewhat too ideal, however we have the reason to believe that it can reflect the real situation in this system since h-BN is free of dangling bonds or surface charge traps. We show in Fig. 2(b) the density-dependent mobility in this SiO_{2}/hBN/Si with several different h-BN thicknesses. The enhancement of mobility is obvious with larger thickness.

Fig. 2.

(Color online) (a) Resistivity dependent on varying thickness of hBN in SiO2/hBN/Si. (b) Density-dependent mobility with three different thicknesses of integrated hBN layer (*T*=0.25 K).

In the case of surface roughness scattering, the advantage of SiO_{2}/hBN/Si is also apparent, attributed to the atomically planar surface of h-BN. Fig. 3(a) clearly exhibits the comparison between these two systems, showing an improvement of mobility in SiO_{2}/hBN/Si. The surface asperity parameters for h-BN are $\mathrm{}\phantom{\rule{0.25em}{0ex}}$Å and $\mathrm{}\phantom{\rule{0.25em}{0ex}}$Å [8], [16] and [17], and we employ the same parameters for undecorated system of SiO_{2}/Si as the previous calculation ($\mathrm{}\phantom{\rule{0.25em}{0ex}}$Å, *d*=15 Å). We integrate the two mechanisms in Fig. 3(b) to show the comparison of total density-dependent mobility in these two systems. With a 50 nm thick h-BN layer, the mobility of SiO_{2}/hBN/Si is almost 10 times higher than the conventional one at the same electron density, showing great potential for high performance devices. An high-*k* dielectric can also enhance mobility through dielectric screening [14]. To show the advantage of high-*k* dielectric, we compare the two MOSFET systems of SiO_{2}/hBN/Si and HfO_{2}/hBN/Si. Upon the same impurity configurations, the calculated mobility for two systems is shown in Fig. 3(c) as a function of h-BN thickness. The obvious enhancement of mobility in HfO_{2}/hBN/Si is observed, comparing with SiO_{2}/hBN/Si due to the different extent of dielectric screening. So we can expect better performance of HfO_{2}/hBN/Si, taking the advantage of both dielectric screening of high-*k* HfO_{2} and smooth, defect-free h-BN surface.

Fig. 3.

(Color online) (a) Surface roughness limited mobility dependent on carrier density in Si-MOSFET with and without hBN decorating. (b) Comparison of total mobility limited by both charged impurity scattering and surface roughness scattering in the MOSFETs of SiO_{2}/Si and SiO_{2}/hBN/Si. (c) Calculated mobility of Si-MOSFETs gated by SiO_{2}/hBN/Si and HfO_{2}/hBN/Si.

In conclusion, we theoretically examine the integration of 2D h-BN into the Si-MOSFETs and compare the mobility of different dielectric systems including SiO_{2}/Si, SiO_{2}/hBN/Si, and HfO_{2}/hBN/Si. The mobility of these systems is mainly limited by charged impurity scattering and surface roughness scattering. We show that, with the integration of 2D hBN, Si-MOSFETs can achieve much higher mobility due to the suppression of various types of scattering. The h-BN layer is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure. The HfO_{2}/hBN/Si gated Si-MOSFET shows the highest mobility taking the advantage of both smooth, defect-free h-BN surface and dielectric screening of high-*k* HfO_{2}. In addition, the room temperature mobility of Si-MOSFETs with the h-BN buffer layer is expected much higher than that of usual Si-MOSFETs because the surface optical phonon scatterings, which are the dominant scattering mechanisms at relatively higher temperature [4], are activated at much higher temperatures due to the relatively higher optical phonon energy of h-BN than that of SiO_{2}.

## Acknowledgments

This work is supported by the Basic Science Research Programs through the National Research Foundation of Korea (NRF): 2009-0083540, 2013-015516, 2014R1A2A2A01006776, and by the Global Frontier Program through the Hybrid Interface Materials (GFHIM) of NRF, funded by the Ministry of Science, ICT & Future Planning: 2013M3A6B1078873.

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